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H V SC AV ER O M A I S IO P L L A N IA BL S N T E
TISP4125H3BJ/TISP4219H3BJ, TISP4125M3BJ/TISP4219M3BJ LCAS RING AND TIP PROTECTION PAIRS BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
*R o
TISP4xxxH3/M3BJ Series for LCAS Protection
Customized Voltage for LCAS Protection Battery-Backed Ringing ............................................. 87 V rms Ground-Backed Ringing ........................................... 101 V rms
SMBJ Package (Top View)
Device `4125 `4219
VDRM V 100 180
V(BO) V 125 219
LCAS TERMINAL TIP RING
MDXXBGE
R(B) 1
2 T(A)
Low Differential Capacitance .................................39 pF max.
Device Symbol
.................................................... UL Recognized Components
T
Rated for International Surge Wave Shapes
ITSP Wave Shape Standard H3 SERIES 2/10 s 8/20 s 10/160 s 10/700 s 10/560 s 10/1000 s GR-1089-CORE IEC 61000-4-5 FCC Part 68 ITU-T K.20/21/45 FCC Part 68 GR-1089-CORE 500 300 250 200 160 100 A M3 SERIES 300 220 120 100 75 50
SD4XAA
R
Terminals T and R correspond to the alternative line designators of A and B
Description
These protector pairs have been formulated to limit the peak voltages on the line terminals of the `7581/2/3 LCAS (Line Card Access Switches) type devices. An LCAS may also be referred to as a Solid State Relay, SSR, i.e. a replacement of the conventional electro-mechanical relay. Overvoltages are normally caused by a.c. power system or lightning flash disturbances which are induced or conducted on to the telephone line. These overvoltages are initially clipped by protector breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. This low-voltage on state causes the current resulting from the overvoltage to be safely diverted through the device. For negative surges, the high crowbar holding current prevents d.c. latchup with the SLIC current, as the surge current subsides. Each protector consists of a symmetrical voltage-triggered bidirectional thyristor. They are guaranteed to voltage limit and withstand the listed international lightning surges in both polarities.
How to Order
For Standard Termination Finish Order As TISP4125H3BJR BJ (J-Bend DO-214AA/SMB) Embossed Tape Reeled TISP4219H3BJR TISP4125M3BJR TISP4219M3BJR For Lead Free Termination Finish Order As TISP4125H3BJR-S TISP4219H3BJR-S TISP4125M3BJR-S TISP4219M3BJR-S
Device TISP4125H3BJ TISP4219H3BJ TISP4125M3BJ TISP4219M3BJ
Package
Carrier
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
TISP4125H3BJ & TISP4219H3BJ
Absolute Maximum Ratings, TA = 25 C (Unless Otherwise Noted)
Rating Repetitive peak off-state voltage, (see Note 1) `4125 `4219 Symbol VDRM Value 100 180 500 300 250 220 200 200 200 160 100 55 60 2.1 400 -40 to +150 -65 to +150 Unit V
Non-repetitive peak on-state pulse current (see Notes 2 and 3) 2/10 s (GR-1089-CORE, 2/10 s voltage wave shape) 8/20 s (IEC 61000-4-5, 1.2/50 s voltage, 8/20 current combination wave generator) 10/160 s (F CC Part 68, 10/160 s voltage wave shape) 5/200 s (VDE 0433, 10/700 s voltage wave shape) 0.2/310 s (I3124, 0.5/700 s voltage wave shape) 5/310 s (I TU-T K.20/21, 10/700 s voltage wave shape) 5/310 s (FTZ R12, 10/700 s voltage wave shape) 10/560 s (F CC Part 68, 10/560 s voltage wave shape) 10/1000 s (GR-1089-CORE, 10/1000 s voltage wave shape) Non-repetitive peak on-state current (see Notes 2, 3 and 4) 20 ms (50 Hz) full sine wave 16.7 ms (60 Hz) full sine wave 1000 s 50 Hz/60 Hz a.c. Initial rate of rise of on-state current, Exponential current ramp, Maximum ramp value < 200 A Junction temperature Storage temperature range NOTES: 1. 2. 3. 4.
ITSP
A
ITSM di T/dt TJ Tstg
A A/s C C
See Applications Information for voltage values at lower temperatures. Initially, the TISP4xxxH3BJ must be in thermal equilibrium with TJ = 25 C. The surge may be repeated after the TISP4xxxH3BJ returns to its initial conditions. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring track widths. See Figure 10 for the current ratings at other durations. Derate current values at -0.61 %/C for ambient temperatures above 25 C.
Recommended Operating Conditions
Component Condition GR-1089-CORE first-level surge survival RS Series current limiting resistor GR-1089-CORE first-level and second-level surge survival K.20, K.21 and K.45 coordination pass with a 400 V primary protector Figure 12, VBAT = -48 V 2.5 V, R1= R2 = 300 , 0 C < TA < +85 C Battery-backed Ground-backed Min 0 0 6 87 101 Typ Max Unit

VRING
AC ringing voltage
V rms V rms
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Electrical Characteristics, TISP4xxxH3, TA = 25 C (Unless Otherwise Noted)
Parameter IDRM V(BO) Repetitive peak offstate current Breakover voltage VD = VDRM dv/dt = 250 V/ms, R SOURCE = 300 dv/dt 1000 V/s, Linear voltage ramp, Maximum ramp value = 500 V di/dt = 20 A/s, Linear current ramp, Maximum ramp value = 10 A dv/dt = 250 V/ms, R SOURCE = 300 I T = 5 A, t W = 100 s I T = 5 A, di/dt = +/-30 mA/ms Linear voltage ramp, Maximum ramp value < 0.85V DRM V D = 50 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V (see Note 5) TA = 85 C rms, VD = 0, rms, VD = -1 V rms, VD = -2 V rms, VD = -50 V rms, VD = -100 V 80 71 65 30 23 Test Conditions TA = 25 C TA = 85 C `4125 `4219 `4125 `4219 0.15 0.15 5 10 90 79 74 35 28 Min Typ Max 5 10 125 219 134 229 0.6 3 0.6 Unit A V
V(BO)
Impulse breakover voltage Breakover current On-state voltage Holding current Critical rate of rise of off-state voltage Off-state current
V
I(BO) VT IH dv/dt ID
A V A kV/s A
Coff
Off-state capacitance
pF
NOTE 5: To avoid possible voltage clipping, the `4125 is tested with V D = -98 V.
Thermal Characteristics
Parameter Test Conditions EIA/JESD51-3 PCB, IT = ITSM(1000) , TA = 25 C, (see Note 6) 265 mm x 210 mm populated line card, 4-layer PCB, IT = ITSM(1000) , TA = 25 C 50 Min Typ Max 113 C/W Unit
R JA Junction to free air thermal resistance
NOTE
6: EIA/JESD51-2 environment and the PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
TISP4125M3BJ & TISP4219M3BJ
Absolute Maximum Ratings, TA = 25 C (Unless Otherwise Noted)
Rating Repetitive peak off-state voltage, (see Note 7) `4125 `4219 Symbol VDRM Value 100 180 300 220 120 110 100 100 100 75 50 30 32 2.1 300 -40 to +150 -65 to +150 Unit V
Non-repetitive peak on-state pulse current (see Notes 8 and 9) 2/10 s (GR-1089-CORE, 2/10 s voltage wave shape) 8/20 s (IEC 61000-4-5, 1.2/50 s voltage, 8/20 current combination wave generator) 10/160 s (F CC Part 68, 10/160 s voltage wave shape) 5/200 s (VDE 0433, 10/700 s voltage wave shape) 0.2/310 s (I3124, 0.5/700 s voltage wave shape) 5/310 s (I TU-T K.20/21, 10/700 s voltage wave shape) 5/310 s (FTZ R12, 10/700 s voltage wave shape) 10/560 s (F CC Part 68, 10/560 s voltage wave shape) 10/1000 s (GR-1089-CORE, 10/1000 s voltage wave shape) Non-repetitive peak on-state current (see Notes 8, 9 and 10) 20 ms (50 Hz) full sine wave 16.7 ms (60 Hz) full sine wave 1000 s 50 Hz/60 Hz a.c. Initial rate of rise of on-state current, Exponential current ramp, Maximum ramp value < 200 A Junction temperature Storage temperature range
ITSP
A
ITSM di T/dt TJ Tstg
A A/s C C
NOTES: 7. See Applications Information for voltage values at lower temperatures. 8. Initially, the TISP4xxxM3BJ must be in thermal equilibrium with TJ = 25 C. 9. The surge may be repeated after the TISP4xxxM3BJ returns to its initial conditions. 10.EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring track widths. See Figure 11 for the current ratings at other durations. Derate current values at -0.61 %/C for ambient temperatures above 25 C.
Recommended Operating Conditions
Component Condition GR-1089-CORE first-level surge survival RS Series current limiting resistor GR-1089-CORE first-level and second-level surge survival K.20, K.21 and K.45 coordination pass with a 400 V primary protector Figure 12, VBAT = -48 V 2.5 V, R1= R2 = 300 , 0 C < TA < +85 C Battery-backed Ground-backed Min 10 12 6 87 101 Typ Max Unit

VRING
AC ringing voltage
V rms V rms
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Electrical Characteristics, TISP4xxxM3, TA = 25 C (Unless Otherwise Noted)
Parameter IDRM V(BO) Repetitive peak offstate current Breakover voltage VD = VDRM dv/dt = 250 V/ms, R SOURCE = 300 dv/dt 1000 V/s, Linear voltage ramp, Maximum ramp value = 500 V di/dt = 20 A/s, Linear current ramp, Maximum ramp value = 10 A dv/dt = 250 V/ms, R SOURCE = 300 IT = 5 A, t W = 100 s IT = 5 A, di/dt = +/-30 mA/ms Linear voltage ramp, Maximum ramp value < 0.85V DRM V D = 50 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V f = 1 MHz, V d = 1 V (see Note 11) TA = 85 C rms, VD = 0, rms, VD = -1 V rms, VD = -2 V rms, VD = -50 V rms, VD = -100 V 62 56 52 26 21 Test Conditions TA = 25 C TA = 85 C `4125 `4219 `4125 `4219 0.15 0.15 5 10 74 67 62 31 25 Min Typ Max 5 10 125 219 132 226 0.6 3 0.6 Unit A V
V(BO)
Impulse breakover voltage Breakover current On-state voltage Holding current Critical rate of rise of off-state voltage Off-state current
V
I(BO) VT IH dv/dt ID
A V A kV/s A
Coff
Off-state capacitance
pF
NOTE 11: To avoid possible voltage clipping, the `4125 is tested with V D = -98 V.
Thermal Characteristics
Parameter Test Conditions EIA/JESD51-3 PCB, IT = ITSM(1000) , TA = 25 C, (see Note 12) 265 mm x 210 mm populated line card, 4-layer PCB, IT = ITSM(1000) , TA = 25 C 52 Min Typ Max 115 C/W Unit
R JA Junction to free air thermal resistance
NOTE 12: EIA/JESD51-2 environment and the PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Parameter Measurement Information
+i ITSP Quadrant I Switching Characteristic
ITSM IT VT IH
V(BO)
I(BO)
-v IDRM
V DRM
VD
ID ID VD V DRM
IDRM +v
I(BO)
IH
V(BO)
VT IT ITSM I
Quadrant III Switching Characteristic ITSP -i
PMXXAAB
Figure 1. Voltage-Current Characteristic for T and R Terminals All Measurements are Referenced to the R Terminal
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
TISP4xxxH3BJ Typical Characteristics
OFF-STATE CURRENT vs JUNCTION TEMPERATURE
100 V D = 50 V 10 |I D| - Off-State Current - A
TCHAG
1.10
NORMALIZED BREAKOVER VOLTAGE vs JUNCTION TEMPERATURE TC4HAF
Normalized Breakover Voltage -25 0 25 50 75 100 125 TJ - Junction Temperature - C 150
1.05
1
0*1
1.00
0*01
0*001
0.95 -25 0 25 50 75 100 125 TJ - Junction Temperature - C 150
Figure 2. ON-STATE CURRENT vs ON-STATE VOLTAGE
200 150 100 IT - On-State Current - A 70 50 40 30 20 15 10 7 5 4 3 2 1.5 1 0.7 1 1.5 2 3 45 V T - On-State Voltage - V 7 10
TC4HACC
Figure 3. NORMALIZED HOLDING CURRENT vs JUNCTION TEMPERATURE TC4HAD
2.0
TA = 25 C tW = 100 s Normalized Holding Current
1.5
1.0 0.9 0.8 0.7 0.6 0.5 0.4 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150
Figure 4.
Figure 5.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
TISP4xxxM3BJ Typical Characteristics
OFF-STATE CURRENT vs JUNCTION TEMPERATURE
100 VD = 50 V Normalized Breakover Voltage 10 |I D| - Off-State Current - A
TCMAG
1.10
NORMALIZED BREAKOVER VOLTAGE vs JUNCTION TEMPERATURE TC4MAF
1.05
1
0*1
1.00
0*01
0*001 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150
0.95 -25 0 25 50 75 100 125 TJ - Junct ion Temperature - C 150
Figure 6.
Figure 7.
ON-STATE CURRENT vs ON-STATE VOLTAGE
100 70 50 40 30 20 15 10 7 5 4 3 2 1.5 1 0.7 1 1.5 2 3 45 VT - On-State Voltage - V 7 10 TA = 25 C tW = 100 s Normalized Holding Current
TC4MACB
2.0
NORMALIZED HOLDING CURRENT vs JUNCTION TEMPERATURE TC4MAD
1.5
IT - On-State Current - A
1.0 0.9 0.8 0.7 0.6 0.5 0.4 -25 0 25 50 75 100 125 TJ - Junction Temperature - C 150
Figure 8.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
Figure 9.
TISP4xxxH3/M3BJ Series for LCAS Protection
Rating Information
TISP4xxxH3BJ NON-REPETITIVE PEAK ON-STATE CURRENT vs CURRENT DURATION
ITSM(t) - Non-Repetitive Peak On-State Current - A ITSM(t) - Non-Repetitive Peak On-State Current - A 30 V GEN = 600 Vrms, 50/60 Hz 20 15 10 9 8 7 6 5 4 3 2 1.5 0*1 RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 C
TI4HAC
TISP4xxxM3BJ NON-REPETITIVE PEAK ON-STATE CURRENT vs CURRENT DURATION
30 20 15 10 9 8 7 6 5 4 3 2 1.5 0*1 1 10 t - Current Duration - s 100 1000
TI4MAC
V GEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 C
1
10
100
1000
t - Current Duration - s
Figure 10.
Figure 11.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
APPLICATIONS INFORMATION
Introduction
These protector pairs have been designed to limit the peak voltages on the line terminals of `7581/7582/7583 LCAS (Line Card Access Switch) parts. An LCAS may also be referred to as a Solid-State Relay, SSR, i.e. a replacement of the conventional electro-mechanical relay. The `7581 LCAS has two solid-state switches which connect the telephone line to the line card SLIC (Subscriber Line Interface Circuit), Figure 12, SW1 and SW2. A further two solid-state switches connect the telephone ringing generator to the line, Figure 12, SW3 and SW4. Applied 5-volt logic signals control the condition of the switches to perform the functions of line disconnect, connection to the SLIC and application of ringing. If excessive long-term overdissipation occurs, a thermal sensor activates thermal shutdown and opens the switches. The SLIC side of switches SW1 and SW2 is limited in voltage by internal protectors Th3 and Th4. The line-side of the LCAS is voltage limited by the two TISP(R) parts.
TISP4125M3 OR TISP4125H3 TIP Th1
RING RELAY
SLIC RELAY
SLIC
SW3
SW1
Th3
Th2 RING SW4
LCAS
Th4
SW2
CONTROL LOGI C
TISP4219M3 OR TISP4219H3
Vbat
AI4XAQ
R2 V RING VBAT SW5a
R1
SW5b
RING GENERATOR
Figure 12. Basic LCAS Arrangement
Additional functions are provided by the `7582 (line test access) and the `7583 (test-in and test-out access). Up to three conventional electromechanical relays may be replaced by the LCAS. The resulting size reduction can double the line density of a line card. This document covers the types of overvoltage protection required by the '7581 LCAS and how the TISP(R) part voltages are selected to provide these requirements. The LCAS '7582 and '7583 are also covered as the additional switches used in these parts are similar to the '7581.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
LCAS Switch Ratings
When a switch is in the off state, the maximum withstand voltage may be set by the switch itself or by the control line to the switch. At 25C, the switch terminal to ground voltage rating for all the switches is 320 V. Switches SW1 to SW3 are bidirectional MOS types and can withstand 320 V between terminals. Switch SW4 is a bidirectional thyristor which is rated at 465 V between terminals. Overcurrents as well as overvoltages occur on telephone lines. In the on state, the thyristor switch, SW4, is capable of withstanding high levels of current overload. For currents above about 200 mA, the MOS switches, SW1 to SW3, will go into a current limited condition. This will cause the voltage to rise across the switch and large amounts of power to be developed. In the longer term, this power loss increases the overall chip temperature. When the temperature exceeds about 125 C, thermal shutdown occurs and the switches are set to the off state. Without power loss, the LCAS will cool. Eventually, the thermal trip will reset, setting the switches back in the high power loss condition again. The cycle of temperature increase, thermal shutdown, temperature decrease and switch re-activation will continue until the overcurrent ceases.
R1 TIP OVERCURRENT PROTECTION
TISP4125M3 OR TISP4125H3
RING RELAY
SLIC RELAY
SLIC
Th1
SW3
SW1
Th3
Th2
Th4
RING R2 SW4 SW2 CONTROL LOGIC TISP4219M3 OR TISP4219H3
Vbat
AI4XAR
GROUND-BACKED RINGING SW5 AS SHOWN +2xV RING TIP WIRE 0 VBAT RING WIRE -2xV RING
R2
R1
BATTERY-BACKED RINGING SW5 OPERATED VBAT + 2xV RING TIP WIRE
2xV RING VBAT SW5b SW5a
0 VBAT
RING GENERAT OR
RING WIRE VBAT - 2xV RING
Figure 13. LCAS Shown with Switch Breakdown Limits
Equivalent Circuit
Figure 13 shows the LCAS switch voltage ratings as breakdown diodes, which must not be allowed to conduct. Each switch has three diodes; one between poles and the other two from each pole to ground. At 25 C, switches SW1 through to SW3 have breakdown diode voltages of 320 V. Switch SW4 has breakdown diode voltage values of 465 V for the one between poles and 320 V for the two diodes connected to ground. Note that only protection to ground is required, as in the limit, the inter-switch voltage limitation of 640 V is the same as the switch to ground limitation of +320 V and -320 V in both polarities.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Protector Voltages
Protector working and protection voltage design calculations for the LCAS are described in the IEEE Std. C62.37.1-2000, IEEE Guide for the Application of Thyristor Surge Protection Devices, pp 40-43. These calculations comprehend: the temprature variation of LCAS voltage ratings, increase in protection voltage with ambient temperature rise, long term a.c. heating and under impulse conditions, decrease in working voltage with ambient temperature fall, ground-backed and battery-backed ringing configurations (see Figure 13). These calculation techniques were used to set the TISP(R) part voltages. Using these TISP(R) parts allows normal system voltage levels of 100 V on TIP and 180 V on RING without clipping at 25 C. At 0 C ambient, these voltage levels become 97 V on TIP and 174 V on RING. Under open circuit line conditions, this means that the peak ringing voltage cannot exceed 174 V for equipment operation down to 0 C ambient. Assuming a battery voltage of 48 V 2.5 V and battery-backed ringing, the maximum peak a.c. ring voltage is 174 V - 50.5 V = 123.5 V or 87 V rms. The working voltage of 97 V on TIP is more than half the 174 V working voltage on RING. As a result, the TIP working voltage does not represent a limitation for systems where the TIP return resistance is equal or less than the RING source resistance. For balanced impedance ground-backed ringing, the maximum peak a.c. ring voltage under short line conditions (short between TIP and RING) is limited by the TIP working voltage of 97 V. In the negative ring polarity, the limit of the voltage is made up from half the battery voltage plus half of the peak a.c. ring voltage. The maximum peak a.c. ring voltage is 2 x (97 - 50.5/2) = 143.5 V or 101 V rms. Line test voltage levels must be considered, whether they be applied by using LCAS switches or separate electro-mechanical relays. For these TISP(R) parts, the applied test voltage should not exceed the lowest working voltage, which is 97 V.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
MECHANICAL DATA
Recommended Printed Wiring Footprint
SMB Pad Size 2.54 (.100)
2.40 (.095)
DIMENSIONS ARE:
MILLIMETERS (INCHES)
2.16 (.085)
MDXX BIA
Device Symbolization Code
Devices will be coded as below. As the device parameters are symmetrical, terminal 1 is not identified.
Device TISP4125H3BJ TISP4219H3BJ TISP4125M3BJ TISP4219M3BJ
Symbolization Code 4125H3 4219H3 4125M3 4219M3
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
MECHANICAL DATA
SMBJ (DO-214AA) Plastic Surface Mount Diode Package
This surface mount package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly.
SMB 4.06 - 4.57 (.160 - .180)
3. 30 - 3. 94 (.130 - .155)
1
2
Index Mark (if needed)
2. 00 - 2.40 (.079 - .094)
0. 76 - 1.52 (.030 - .060) 5. 21 - 5.59 (.205 - .220)
MILLIMETERS (INCHES)
1. 90 - 2.10 (.075 - .083)
0. 10 - 0. 20 (.004 - .008)
1. 96 - 2. 32 (.077 - .091)
DIMENSIONS ARE:
MDXXBHAA
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
MECHANICAL DATA
Tape Dimensions
SMB Package Single-Sprocket Tape
3. 90 - 4.10 (.154 - .161 ) 1. 95 - 2.05 (.077 - .081)
1. 55 - 1.65 (.061 - .065 ) 1. 65 - 1.85 (.065 - .073 ) 0. 40 MAX . (.016)
5. 45 - 5.55 (.215 - .219 ) 11.70 - 12.30 (.461 - .484 )
8. 20 MAX . (.323)
7. 90 - 8.10 (.311 - .319 ) Direction of Feed
1. 5 MIN . (.059) Carrier Tape Embossment 20
0 MIN .
Cover Tape 4. 5 MAX . (.177)
Maximium component rotation
Index Mark (if needed)
Typical component cavity center line Typical component center line
NOTES: A. The clearance between the component and the cavity must be within 0.05 mm (.002 in) MIN. to 0.65 mm (.026 in) MAX. so that the component cannot rotate more than 20 within the determined cavity. B. Taped devices are supplied on a reel of the following dimensions: Reel diameter: 330 mm 3.0 mm (12.99 in .118 in) Reel hub diameter: 75 mm (2.95 in) MIN. Reel axial hole: 13.0 mm 0.5 mm (.512 in .020 in) C. 3000 devices are on a reel.
MDXXBJA
"TISP" is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office. "Bourns" is a registered trademark of Bourns, Inc. in the U.S. and other countries.
JUNE 2001 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.

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